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ds04-22002-1e fujitsu semiconductor data sheet assp communication control ieee 1394 bus controller (for dvc) mb86615 n description the mb86615 is 1394 serial bus controller compatible with the ieee 1394 firewire standard (ieee standard 1394-1995). one built-in port plus a differential transceiver and comparator are provided to enable formation of networks in a 1394 cable environment. the mb86615 supports s100 data transfer speeds. by integrating the physical layer and link layer on one chip, the mb86615 is designed to reduce mounting area as well as power consumption. the mb86615 has an exclusive data port for isochronous transfer, provides automatic packetizing for sending and separation of header and data units at receiving, and is optimized for continuity of transfer processing. the mb86615 supports dvc av/c protocols, and includes the necessary built-in automatic operations and csrs for providing the necessary operations for dvc data transfer. n features ? compatible with ieee 1394 high-performance serial bus standards ? physical layer and link layer integrated on one chip ? 1 cable ports ? supports s100 transfer speed (98.304 mbit/sec) ? 3.3v single power supply operation ? built-in pll (for crystal oscillator) for internal clock signal generation ? power saving modes 1) forced sleep mode at instruction from mpu 2) automatic sleep mode for non-connected ports ? header and data units automatically separated at receiving and automatic packetizing for sending ? supports cycle master functions (continued) n packages 100-pin plastic lqfp (fpt-100p-m05) 120-pin plastic fbga (bga-120p-m01)
2 mb86615 (continued) ? built-in csrs to provide isochronous resource manager functions ? 32-bit crc generation and check functions ? general purpose port for asynchronous transfer and control (16-bit mpu/dma common bus) ? exclusive built-in ports for isochronous transfer (8-bit bus) ? built-in crss and automatic processes to support dvc 1) automatic separation of cip headers at receiving, and automatic packetizing at sending. 2) automatic generation and match detection of time stamp by fp signal. 3) dbc area automatic increment function 4) no-data packet sending and receiving 5) on-chip pcr (input/output 1 channel each) 6) each csr with automatic c&s lock processing and read processing ? compatible with 4-core cable ? packages: lqfp-100, fbga-120
3 mb86615 n pin assignments 1. lqfp-100 reset int v dd v ss ale d15 d14 d13 d12 d11 d10 d9 d8 v dd v ss d7 d6 ad5 ad4 ad3 ad2 ad1 d0 v dd v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (fpt-100p-m05) av dd av ss n.c. n.c. n.c. n.c. av dd av ss n.c. av dd av ss n.c. av ss av dd tpa tpb tpa tpb av ss av dd tpbias av ss av dd roi n.c. 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 mode0 mode1 test5 fp icrce iv ilwre idir iclk v dd v ss id0 id1 id2 id3 id4 id5 id6 id7 test4 test3 v ss v dd test2 test1 99 100 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 av dd av ss rop chpo vcoin av dd av ss testp x1 x0 v ss v dd dack dreq n.c. a1 a2 a3 a4 a5 cs v ss v dd rd (r/w) wr (ds) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
4 mb86615 2. fbga-120 13 12 11 10 9 8 7 6 5 4 3 2 1 n.c. av dd av ss vcoin testp xo dack n.c. a3 a5 v dd n.c. wr (ds ) n n.c. roi n.c. chpo av ss x1 v dd dreq a2 a4 v ss rd (r/w) v ss m av dd av ss tp- bias rop av dd n.c. v ss n.c. a1 n.c. cs n.c. v dd l av dd av ss tpb d0 ad1 ad2 k tpa tpb n.c. ad3 ad4 ad5 j tpa av dd av ss d6 n.c. d7 i n.c. n.c. av ss top view v ss v dd d8 h av dd n.c. n.c. n.c. d9 d10 g av ss av dd n.c. d11 d12 n.c. e n.c. n.c. n.c. d13 d14 d15 d n.c. av ss test3 id7 id4 v ss idir iv test5 ale v ss v dd c av dd test2 v ss n.c. id5 id0 iclk n.c. fp n.c. int n.c. b test1 n.c. v dd test4 id6 id3 v dd ilwre i crce mode 0 mode 1 reset a id1 id2 n.c. 1 pin
5 mb86615 n pin list 1. lqfp-100 (continued) no. i/o pin name no. i/o pin name 1 id reset 34 id a2 2 o int 35 id a1 3 v dd 36 iu pmode 4 v ss 37 o ctr 5 id ale 38 o oclk 6 id/o d15 39 v dd 7 id/o d14 40 v ss 8 id/o d13 41 i/o x0 9 id/o d12 42 i x1 10 id/o d11 43 testp 11 id/o d10 44 av ss 12 id/o d9 45 av dd 13 id/o d8 46 i vcoin 14 v dd 47 o chpo 15 v ss 48 o rop 16 id/o d7 49 av ss 17 id/o d6 50 av dd 18 id/o ad5 51 n.c. 19 id/o ad4 52 o ro1 20 id/o ad3 53 av dd 21 id/o ad2 54 av ss 22 id/o ad1 55 o tapbias1 23 id/o d0 56 av dd 24 v dd 57 av ss 25 v ss 58 i/o tpb1 26 id wr (xds) 59 i/o tpa1 27 id rd (r/w) 60 i/o tpb1 28 v dd 61 i/o tpa1 29 v ss 62 ro0 30 id cs 63 av dd 31 id a5 64 o av ss 32 id a4 65 ro0 33 id a3 66 av dd 34 v dd 57 av dd 35 v ss 58 i/o tpb1 n pin list 1. lqfp-100 (continued) no. i/o pin name no. i/o pin name 1 id reset 34 id a2 2 o int 35 id a1 3 v dd 36 iu pmode 4 v ss 37 o ctr 5 id ale 38 o oclk 6 id/o d15 39 v dd 7 id/o d14 40 v ss 8 id/o d13 41 i/o x0 9 id/o d12 42 i x1 10 id/o d11 43 testp 11 id/o d10 44 av ss 12 id/o d9 45 av dd 13 id/o d8 46 i vcoin 14 v dd 47 o chpo 15 v ss 48 o rop 16 id/o d7 49 av ss 17 id/o d6 50 av dd 18 id/o ad5 51 n.c. 19 id/o ad4 52 o ro1 20 id/o ad3 53 av dd 21 id/o ad2 54 av ss 22 id/o ad1 55 o tapbias1 23 id/o d0 56 av dd 24 v dd 57 av ss 25 v ss 58 i/o tpb1 26 id wr (xds) 59 i/o tpa1 27 id rd (r/w) 60 i/o tpb1 28 v dd 61 i/o tpa1 29 v ss 62 ro0 30 id cs 63 av dd 31 id a5 64 o av ss 32 id a4 65 ro0 33 id a3 66 av dd 34 v dd 57 av dd 35 v ss 58 i/o tpb1 n pin list 1. lqfp-100 (continued) no. i/o pin name no. i/o pin name 1 i reset 36 n.c. 2 o int 37 o dreq 3 v dd 38 i dack 4 v ss 39 v dd 5 i ale 40 v ss 6 iu/o d15 41 i/o x0 7 iu/o d14 42 i x1 8 iu/o d13 43 o testp 9 iu/o d12 44 av ss 10 iu/o d11 45 av dd 11 iu/o d10 46 i vcoin 12 iu/o d9 47 o chpo 13 iu/o d8 48 o rop 14 v dd 49 av ss 15 v ss 50 av dd 16 iu/o d7 51 n.c. 17 iu/o d6 52 o roi 18 iu/o ad5 53 av dd 19 iu/o ad4 54 av ss 20 iu/o ad3 55 o tpbias 21 iu/o ad2 56 av dd 22 iu/o ad1 57 av ss 23 iu/o d0 58 i/o tpb 24 v dd 59 i/o tpa 25 v ss 60 i/o tpb 26 i wr (ds ) 61 i/o tpa 27 i rd (r/w) 62 av dd 28 v dd 63 av ss 29 v ss 64 n.c. 30 i cs 65 av ss 31 i a5 66 av dd 32 i a4 67 n.c. 33 i a3 68 av ss 34 i a2 69 av dd 35 i a1 70 n.c.
6 mb86615 (continued) no. i/o pin name no. i/o pin name 71 n.c. 86 i/o id3 72 n.c. 87 i/o id2 73 n.c. 88 i/o id1 74 av ss 89 i/o id0 75 av dd 90 v ss 76 iu/o test1 91 v dd 77 iu/o test2 92 i iclk 78 v dd 93 i idir 79 v ss 94 o ilwre 80 iu/o test3 95 i iv 81 iu/o test4 96 o i crce 82 i/o id7 97 i/o fp 83 i/o id6 98 o test5 84 i/o id5 99 i mode0 85 i/o id4 100 i mode1
7 mb86615 2. fbga-120 (continued) pin no. ball no. i/o pin name pin no. ball no. i/o pin name pin no. ball no. i/o pin name 1 a1 i reset 37 n4 i a5 73 h13 i/o tpa 2 b1 n.c. 38 m4 i a4 74 h12 av dd 3 b2 o int 39 l4 n.c. 75 h11 av ss 4 c1 v dd 40 n5 i a3 76 g13 n.c. 5 c2 v ss 41 m5 i a2 77 g12 n.c. 6 c3 i ale 42 l5 i a1 78 g11 av ss 7 d1 iu/o d15 43 n6 n.c. 79 f13 av dd 8 d2 iu/o d14 44 m6 o dreq 80 f12 n.c. 9 d3 iu/o d13 45 l6 n.c. 81 f11 n.c. 10 e1 n.c. 46 n7 i dack 82 e13 av ss 11 e2 iu/o d12 47 m7 v dd 83 e12 av dd 12 e3 iu/o d11 48 l7 v ss 84 e11 n.c. 13 f1 iu/o d10 49 n8 i/o x0 85 d13 n.c. 14 f2 iu/o d9 50 m8 i x1 86 d12 n.c. 15 f3 n.c. 51 l8 n.c. 87 d11 n.c. 16 g1 iu/o d8 52 n9 o testp 88 c13 n.c. 17 g2 v dd 53 m9 av ss 89 c12 av ss 18 g3 v ss 54 l9 av dd 90 b13 av dd 19 h1 iu/o d7 55 n10 i vcoin 91 a13 iu/o test1 20 h2 n.c. 56 m10 o chpo 92 a12 n.c. 21 h3 iu/o d6 57 l10 o rop 93 b12 iu/o test2 22 j1 iu/o ad5 58 n11 av ss 94 a11 v dd 23 j2 iu/o ad4 59 m11 n.c. 95 b11 v ss 24 j3 iu/o ad3 60 n12 av dd 96 c11 iu/o test3 25 k1 iu/o ad2 61 n13 n.c. 97 a10 iu/o test4 26 k2 iu/o ad1 62 m13 n.c. 98 b10 n.c. 27 k3 iu/o d0 63 m12 o roi 99 c10 i/o id7 28 l1 v dd 64 l13 av dd 100 a9 i/o id6 29 l2 n.c. 65 l12 av ss 101 b9 i/o id5 30 m1 v ss 66 l11 o tpbias 102 c9 i/o id4 31 n1 i wr (ds ) 67 k13 av dd 103 a8 i/o id3 32 n2 n.c. 68 k12 av ss 104 b8 i/o id2 33 m2 i rd (r/w) 69 k11 i/o tpb 105 c8 i/o id1 34 n3 v dd 70 j13 i/o tpa 106 a7 n.c. 35 m3 v ss 71 j12 i/o tpb 107 b7 i/o id0 36 l3 i cs 72 j11 n.c. 108 c7 v ss
8 mb86615 (continued) pin no. ball no. i/o pin name pin no. ball no. i/o pin name pin no. ball no. i/o pin name 109 a6 v dd 113 b5 n.c. 117 c4 o test5 110 b6 i iclk 114 c5 i iv 118 a3 i mode0 111 c6 i idir 115 a4 o i crce 119 b3 n.c. 112 a5 o ilwre 116 b4 i/o fp 120 a2 i mode1
9 mb86615 n pin description 1. 1394 interface 2. isochronous-data interface (continued) pin name i/o function tpa i/o 1394 cable port tpa positive signal i/o pin tpa i/o 1394 cable port tpa negative signal i/o pin tpb i/o 1394 cable port tpb positive signal i/o pin tpb i/o 1394 cable port tpb negative signal i/o pin tpbias o 1394 cable port common voltage reference voltage output pin roi o connect to gnd through 4.7 k w resistance pin name i/o function iclk i isochronous data interface clk signal input pin (4 mhz to 16 mhz). idir i isochronous transfer transmission/reception switching signal input pin. 0 input: the device clears the iso-fifo buffer and enters the transmission mode. the device asserts the ilwre signal and starts transmission after receiving one packet of data according to the data-length setting (bank 0: 10h). 1 input: the device clears the iso-fifo buffer and enters the reception mode. if any packet being transmitted exists, the device enters the reception mode after completing transmission of the packet. the ilwre signal is asserted upon reception of one packet. note: the idir signal should normally be left at 1 and switched to 0 only for transmission. ilwre o iso-fifo access enable signal output pin. transmission mode: the signal is asserted when the fifo buffer is not full. the signal is negated when the fifo buffer becomes full. when it is negated, data is accepted only up to the rising edge of the next iclk signal. when a bus reset is detected, the signal is negated after accepting data of up to the packet boundary. after the bus reset, the signal is asserted again upon completion of transmission of one source packet remaining in the fifo buffer. reception mode: the signal is asserted upon completion of one packet of data. the signal is negated once when one packet of data is read from the fifo buffer and asserted back if the fifo buffer still contains any packet of data which has been received completely. id7 to id0 i/o isochronous transfer data input/output bits. (msb is id7, lsb is id0) iv i id7 to id0 enable signal input pin transmission mode: while the iv signal is active, data from the id7 to id0 pins is loaded into the iso-fifo buffer at the rising edge of the iclk signal. reception mode: while the signal becomes active, the device starts sending data from the iso-fifo buffer to the id7 to id0 pins. data is then switched at the rising edge of the iclk signal.
10 mb86615 (continued) 3. system interface pin name i/o function icrec o this pin outputs a signal indicating that data sent in the reception mode is data in a packet from which a data-crc error has been detected. fp i/o time stamp trigger signal i/o pin. transmission mode: this pin inputs the time stamp trigger signal. the value in the internal cycle timer register is fetched upon detection of the falling edge of the fp signal. reception mode: time stamp match detection signal output pin. pin name i/o function cs i input pin for signals used by the mpu to select the mb86615 as an i/o device. a5 to a1 i address input pins for internal register selection. valid only in non-multiplexed mode. if multiplexed mode is selected these pins should be fixed at 0. d15 to d6, d0 i/o 16-bit data bus input/output pins (msb is d15, lsb is d0). ad5 to ad1 i/o 16-bit data bus input/output pins (msb is ad5, lsb is ad1). used for address input signals when multiplexed mode is selected. rd (r/w) i 80-series mode: read strobe signal input pin, used to output data from the mb86615 to the data bus. 68-series mode: control signal input pin, used for data input/output operations to the mb86615. wr (ds ) i 80-series mode: write strobe signal input pin, used to input data from the data bus to the mb86615. 68-series mode: ds signal input pin, output when data bus is enabled. ale i ale signal input pin, for signal output when addresses are enabled in multiplexed mode. in non-multiplexed mode, this signal should be fixed at 0. dreq o this pin outputs the dma transfer request signal to the dmac for asynchronous transfer in dma mode. the signal requests dma transfer between the device and memory. dack i this pin inputs the dma enable signal from the dmac for asynchronous transfer in dma mode. int o interrupt output pin.
11 mb86615 4. other pin name i/o function x0 i/o external crystal connection pins for oscillator circuits. x1 i vcoin i vco input pin for internal pll. chpo o charge pump output pin for internal pll. rop o connect to gnd through 4.7 k w resistance. reset i reset signal input pin. the device enters the forced sleep mode automatically upon detection of the reset signal asserted. mode0 i input 0 for 80-series mode. input 1 for 68-series mode. mode1 i input 0 for non-multiplexed mode. input 1 for multiplexed mode. testp o test pin. do not connect. test1 to test4 iu/o test pin. do not connect. test5 o test pin. do not connect. av dd analog power supply av ss analog ground v dd digital power supply v ss digital ground n.c. unused pin. do not connect.
12 mb86615 n block diagram idir iso sending packet processing async send-only fifo (128 byte) async receive-only fifo (128 byte) async sending packet processing async receiving packet processing iso receiving packet processing link layer control circuit cycle master transaction control circuit block dedicated transaction control circuit block pll circuit phy layer control circuit iclk ilwre id7 to id0 iv cs a5 to a1 d15 to d6, d0 ad5 to ad1 rd (r/w) wr (ds) ale int tpa tpa tpb tpb tpbias isochronous interface system & asynchronous interface 1394 interface iso sending/receiving fifo (1kb) register block csr fp icrce dreq dack
13 mb86615 n block descriptions ? phy layer control circuit this block contains the ieee 1394 physical layer control circuits. both asynchronous transfer and isochronous transfer in a cable environment are supported. the transfer speed is 100 mbit/sec. one analog transceiver/receiver ports are built-in. this block provides bus status monitoring initialization operation after a bus reset is applied, as well as arbitration and encoding/decoding functions for data sending and receiving. ? link layer control circuit this block controls the generation and transfer of ieee 1394 standard packets. 32-bit crc generation and checking is performed for packet headers and data. a 32-bit cycle timer register is built-in to provide cycle master functions. ? sending/receiving fifo contains built-in 1-byte fifo areas, used for isochronous transfer for both sending and receiving. contains independent sending and receiving 128-byte fifo areas for asynchronous transfer. ? packet processing sending: performs packetizing of headers, data and crc. automatically generates and attaches crc. receiving: separates 1394 packet headers and data, strips crc. ? transaction control circuit block this block controls the 1394 bus protocol based on a variety of instructions. ? dedicated transaction circuit block this block packetizes data from the isochronous interface for dvc and rebuilds received data for the isochronous interface in conjunction with the packet processing block. ? register block this block contains various device control registers, as well as registers for setting parameters required for transfer, dvc registers and csr. the built-in csr provides isochronous resource manager functions. ? pll circuit this block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating clock and transfer clock signals. reference oscillator frequency: 8.192 mhz.
14 mb86615 n absolute maximum ratings *1: voltage values are based on vss = 0 v. *2: not warranted for continuous operation. *3: normal output current flow (minimum at vo = 0 v, maximum at vo = v dd ). *4: 50 ns or less. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage values are based on vss = 0 v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage* 1 v dd v ss C 0.5 4.0 v input voltage* 1 v i v ss C 0.5 v dd + 0.5 v output voltage* 1 v o v ss C 0.5 v dd + 0.5 v strage temperature tst C55 +125 c operating temperature* 2 top C40 +85 c output current* 3 i o C14 +14 ma overshoot* 4 v dd + 1.0 v undershoot* 4 v ss C 1.0 v parameter symbol value unit min. max. power supply voltage* v dd 3.0 3.6 v h level input voltage cmos input v ih v dd 0.65 v dd v l level input voltage cmos input v il v ss v dd 0.25 v differential input voltage (for data transfer) cable input v id 142 260 mv differential input voltage (for arbitration) cable input v ida 173 260 mv common mode input voltage cable input v cm 1.165 2.515 v receiving input jitter cable input 1.08 ns receiving input skew cable input 0.8 ns output current cmos output i oh /i ol C4 +4 ma tpbias iot C2 +10 ma operating temperature ta 0 +70 c
15 mb86615 n electrical characteristics 1. dc characteristics 1.1 1394 interface driver (v dd = 3 to 3.6 v , v ss = 0 v, ta = 0 to +70 c) 1.2 1394 interface - comparator (v dd = 3 to 3.6 v , v ss = 0 v, ta = 0 to +70 c) parameter symbol conditions value unit min. max. differential output voltage v od r 1 = 56 w 172 265 mv common phase current i cm driver enabled C0.81 0.44 ma off state voltage v off driver disabled 20 mv tpbias output voltage v o 1.665 2.015 v parameter symbol conditions value unit min. max. common phase input current i ic driver disabled C20 20 m a arbitration comparator h level detection offset v sch driver disabled 168 mv arbitration comparator z level detection offset v scz driver disabled C30 30 mv arbitration comparator l level detection offset v scl driver disabled C168 mv port status comparator disconnection detect voltage v sd driver disabled 0.6 v port status comparator connection detect voltage v sc driver disabled 1.0 v
16 mb86615 1.3 system interface, etc (v dd = 3 to 3.6 v , v ss = 0 v, ta = 0 to +70 c) parameter symbol conditions value unit min. typ. max. h level input voltage v ih cmos v dd 0.65 v dd v l level input voltage v il cmos v ss v dd 0.25 v h level output voltage v oh i oh = C4 ma v dd C 0.5 v dd v l level output voltage v ol i ol = +4 ma v ss 0.4 v input leak current input pins i li v i = 0v to v dd C5 5 m a 3-state pin input i lz C5 5 m a input pull-up resistance rp v ih = 0 25 50 200 k w power supply current i dd1 1394 port connected 200 ma i dd0 1394 port non connected 180 ma i dds forced sleep 30 ma
17 mb86615 2. ac characteristics 2.1 1394 driver * : 10 to 90% value. 2.2 system clock parameter symbol value unit min. max. sending jitter t jt 0.8 ns sending skew t sk 0.8 ns sending rise time* conditions c l = 10 pf. r l = 56 w t dr 3.2ns sending fall time* t df 3.2ns parameter symbol value unit min. typ. max. clock frequency f c 8.191992 8.192 8.192008 mhz clock cycle time t clf 1/fc ns clock pulse width high t clch 50 ns low t clcl 50 ns clock rise time t cr 5 ns clock fall time t cf 5 ns 0. 65 v dd 0. 25 v dd clk t clch t clf t cf t clcl t cr
18 mb86615 2.3 system reset parameter symbol value unit min. max. reset (reset) l level pulse width t wrsl 4 tclf ns t wrsl reset
19 mb86615 2.4 mpu interface (1) 68-series register write operation (multiplexed) parameter symbol value unit min. max. address setup time t awsm 10 ns address hold time t awhm 10 ns cs setup time t cwsm 20 ns cs hold time t cwhm 10 ns r/w setup time t rwsm 20 ns r/w hold time t rwhm 10 ns ale h level pulse width t ale 15 ns ale fall to ds fall time t dwd 15 ns ds l level pulse width t dsm 40 ns data setup time t dwsm 10 ns data hold time t dwhm 0ns ds rise to ale rise time t lwd 20 ns cs t cwsm t cwhm t rwhm t lwd t rwsm t ale t dwd t dsm t awsm t awhm t dwsm t dwhm r/w ale ds d15 to d6, d0 ad5 to ad1 address data
20 mb86615 (2) 68-system register read operation (multiplexed) parameter symbol value unit min. max. address setup time t arsm 10 ns address hold time t arhm 10 ns cs setup time t crsm 20 ns cs hold time t crhm 10 ns r/w setup time t rwsm 20 ns r/w hold time t rwh 10 ns ale h level pulse width t ale 15 ns ale fall to ds fall time t drd 15 ns ds l level pulse width t dsm 40 ns data output definition time t rldm 40ns data output disabled time t rhdm 5ns ds rise to ale rise time t lrd 20 ns cs t crsm t crhm t rwh t lrd t rwsm t ale t drd t arsm t arhm t rldm t dsm t rhdm r/w ale ds d15 to d6, d0 ad5 to ad1 address defined data
21 mb86615 (3) 68-series register write operation (non-multiplexed) parameter symbol value unit min. max. address setup time t aws 10 ns address hold time t awh 20 ns cs setup time t cws 20 ns cs hold time t cwh 10 ns r/w setup time t rws 20 ns r/w hold time t rwh 10 ns ds l level pulse width t ds 40 ns data setup time t dws 40 ns data hold time t dwh 0ns cs t aws t awh t cws t rws t ds t dws t dwh t cwh t rwh r/w ds a5 to a0 d15 to d6, d0 ad5 to ad1 data
22 mb86615 (4) 68-series register read operation (non-multiplexed) parameter symbol value unit min. max. address setup time t ars 10 ns address hold time t arh 20 ns cs setup time t crs 20 ns cs hold time t crh 10 ns r/w setup time t rws 20 ns r/w hold time t rwh 10 ns ds l level pulse width t ds 40 ns data output definition time t rld 40ns data output disabled time t rhd 5ns cs t ars t arh t crs t rws t ds t rld t rhd t crh t rwh r/w ds d15 to d6, d0 ad5 to ad1 defined data a5 to a0 address
23 mb86615 (5) 80-series register write operation (multiplexed) parameter symbol value unit min. max. address setup time t awsm 10 ns address hold time t awhm 10 ns cs setup time t cwsm 20 ns cs hold time t cwhm 10 ns ale h level pulse width t ale 15 ns ale fall to wr fall time t dwd 15 ns wr l level pulse width t wrm 40 ns data setup time t dwsm 40 ns data hold time t dwhm 0ns wr rise to ale rise time t lwd 20 ns cs ale wr d15 to d6, d0 ad5 to ad1 t cwsm t cwhm t dwhm t dwsm t wrm t ale t dwd t lwd t awsm t awhm address data
24 mb86615 (6) 80-series register read operation (multiplexed) parameter symbol value unit min. max. address setup time t arsm 10 ns address hold time t arahm 10 ns cs setup time t crsm 20 ns cs hold time t crhm 10 ns ale h level pulse width t ale 15 ns ale fall to rd fall time t drd 15 ns rd l level pulse width t rdm 40 ns data output definition time t rldm 40ns data output disabled time t rhdm 5ns rd rise to ale rise time t lrd 20 ns cs ale rd d15 to d6, d0 ad5 to ad1 t crsm t crhm t rhdm t rldm t rdm t ale t drd t lrd t arsm t arahm address defined data
25 mb86615 (7) 80-series register write operation (non-multiplexed) parameter symbol value unit min. max. address setup time t aws 10 ns address hold time t awh 20 ns cs setup time t cws 20 ns cs hold time t cwh 10 ns wr l level pulse width t wr 40 ns data setup time t dws 40 ns data hold time t dwh 0ns t aws t cws t wr t awh t cwh t dwh t dws cs wr a5 to a0 d15 to d6, d0 ad5 to ad1 address data
26 mb86615 (8) 80-series register read operation (non-multiplexed) (9) int signal operation note: this specification applies only to reading of the last data from the interrupt holding register. for other read-related specifications, conform to the respective specifications for individual modes. parameter symbol value unit min. max. address setup time t ars 10 ns address hold time t arh 20 ns cs setup time t crs 20 ns cs hold time t crh 10 ns rd l level pulse width t rd 40 ns data output definition time t rld 40ns data output disabled time t rhd 5ns parameter symbol value unit min. max. interrupt read operation to int signal negate t intd 100 ns t ars t crs t rd t arh t crh t rhd t rld cs rd a5 to 0 d15 to d6, d0 ad5 to ad1 address defined data t intd rd, ds int
27 mb86615 2.5 dma access (1) 68-series dma write operation parameter symbol value unit min. max. dreq h to dack l t dhal 0ns ds h to dreq l t dhdl 30ns dack setup time t daws 20 ns dack hold time t dawh 0ns r/w setup time t drws 20 ns r/w hold time t drwh 10 ns ds l level pulse width t dds 40 ns ds h level pulse width t ddsh 30 ns input data setup time t ddws 30 ns input data hold time t ddwh 0ns dreq dack r/w ds t dhal t dhdl t daws t dawh t drwh t drws t dds t ddsh t ddws t ddwh d15 to d6, d0 ad5 to ad1 data data
28 mb86615 (2) 68-series dma read operation parameter symbol value unit min. max. dreq h to dack l t dhal 0ns ds h to dreq l t dhdl 30ns dack setup time t dars 20 ns dack hold time t darh 0ns r/w setup time t drws 20 ns r/w hold time t drwh 10 ns ds l level pulse width t dds 40 ns ds h level pulse width t ddsh 30 ns data output definition time t drld 40ns data output disabled time t drhd 5ns dreq dack r/w ds t dhal t dhdl t dars t darh t drwh t drws t dds t ddsh t drld t drhd d15 to d6, d0 ad5 to ad1 defined data defined data
29 mb86615 (3) 80-series dma write operation parameter symbol value unit min. max. dreq h to dack l t dhal 0ns wr h to dreq l t dhdl 30ns dack setup time t daws 20 ns dack hold time t dawh 0ns wr l level pulse width t dwr 40 ns wr h level pulse width t dwrh 30 ns input data setup time t ddws 30 ns input data hold time t ddwh 0ns dreq dack wr t dhal t dhdl t daws t dawh t dwr t dwrh t ddws t ddwh d15 to d6, d0 ad5 to ad1 data data
30 mb86615 (4) 80-series dma read operation parameter symbol value unit min. max. dreq h to dack l t dhal 0ns rd h to dreq l t dhdl 30ns dack setup time t dars 20 ns dack hold time t darh 0ns rd l level pulse width t drd 40 ns rd h level pulse width t drdh 30 ns data output definition time t drld 40ns data output disabled time t drhd 5ns dreq dack rd t dhal t dhdl t dars t darh t drd t drdh t drld t drhd d15 to d6, d0 ad5 to ad1 defined data defined data
31 mb86615 2.6 isochronous interface 2.6.1 iclk parameter symbol value unit min. max. clock frequency 4 16 mhz clock cycle time t iclk 62.5 250 ns clock h level pulse width t iclh 20 ns clock l level pulse width t icll 20 ns clock rise time t icr 7ns clock fall time t icf 7ns iclk 0. 25 v dd 0. 65 v dd t iclh t icf t icr t iclk t icll
32 mb86615 2.6.2 sending operation (1) start sending operation parameter symbol value unit min. max. idir fall to ilwre fall time t sdir t iclk + 125 ns iclk rise to ilwre fall time t sidir 40ns ilwre fall to iv fall time t iliv 0ns iv setup time t siv 40 ns data setup time t sd 20 ns data hold time t hd 0ns iclk idir ilwre iv t sdir t iliv t siv t sd t hd 123 t sidir id7 to id0
33 mb86615 (2) end sending operation parameter symbol value unit min. max. i v rise to idir rise time t hdir 0ns idir rise to i lwre rise time t dwr 1 t iclk + 40 ns iclk rise to i lwre rise time t swdir 40ns idir rise to idir fall time t dirh 250 m s iclk idir ilwre iv n - 1 n n + 1 t hdir t dirh t dwr t swdir id7 to id0
34 mb86615 (3) iv temporary negation in sending operation parameter symbol value unit min. max. iv hold time t hiv 0t iclk C 40 ns date setup time t sd 20 ns data hold time t hd 0ns iclk idir ilwre iv n - 1 n n + 1 t hiv t sd t hd id7 to id0
35 mb86615 (4) negating ilwre during transmission (with a bus reset detected or the fifo buffer full) note: the ilwre signal is negated to stop writing data to be transmitted in either of the following cases in the transmission mode (1) when the iso transmission/reception fifo buffer becomes full (the ilwre signal is negated in synchronization with the last iclk signal generated before the fifo buffer becomes full. note, however, that this condition does not negate the ilwre signal if the point-rcc bit (bit 7) in the iso-fifo control register (address 0eh) has been set to 1. (2) when a bus reset is detected (the ilwre signal is negated in synchronization with the last iclk signal generated before the fifo buffer loads one packet of data after detection of the bus reset.) the ilwre signal is asserted back when transmission of one packet of data to the 1394 bus is completed. parameter symbol value unit min. max. iclk rise to ilwre rise time t hwrl 40ns ilwre rise to i v rise time t remiv t iclk 2 t iclk C 40 ns iclk rise to ilwre fall time t hwrh 40ns iclk idir ilwre iv valid valid valid ignore t hwrl t hwrh t remiv id7 to id0
36 mb86615 (5) switch to transmission from reception in process (6) fp input timing parameter symbol value unit min. max. idir fall to ilwre rise time t dlwrh t iclk + 40 ns idir fall to ilwre fall time t dlwrl 2 t iclk + 40 ns parameter symbol value unit min. max. fp l level pulse width t fpl 100 ns fp h level pulse width t fph 125 m s fp h detection to ctr value load 80 150 ns iclk idir ilwre t dlwrh t dlwrl fp t fpl t fph
37 mb86615 2.6.3 receiving operation (1) start receiving operation * : the i crc e signal is output when a crc error is detected in receiving data. parameter symbol value unit min. max. iclk rise to ilwre fall t wreh 40ns i v setup time t siv 40 ns data output definition time t dz 40ns data output disable time t d 10 40 ns i v fall to i crc e fall time* t errl 40ns iclk idir ilwre iv hi - z123 icrce t wreh t siv t dz t errl t d id7 to id0
38 mb86615 (2) end receiving operation *1: this device negates the ilwre signal upon completion of reading each packet of data. *2: the icrce signal is asserted only when a crc error is detected in data received. parameter symbol value unit min. max. iclk rise to ilwre rise t wrel 40ns data output disable time t zd 050ns ilwre negate time* 1 t wreh 6 t iclk ns i v rise to i crc e rise time* 2 t errh 40ns iclk idir ilwre iv hi - z n - 2n - 1n icrce t wrel t wreh t zd t errh id7 to id0
39 mb86615 (3) iv temporary negation in receiving operation parameter symbol value unit min. max. iv rise to iclk rise t hiv 40 ns i v rise to i crc e rise time t errh 40ns i v fall to i crc e fall time t errl 40ns iclk idir ilwre iv hi - z n - 3n - 2n - 1 icrce t hiv t errh t errl id7 to id0
40 mb86615 (4) fp signal output parameter symbol value unit min. max. idir fall to fp output enable t zfp 40ns fp l level pulse width t fpw 600 730 ns time stamp match detect to fp output 40 ns idir fp hi - z t zfp t fpw
41 mb86615 2.6.4 clearing the iso transmission/reception fifo buffer using the fifo-clr bit the iso transmission/reception fifo buffer is cleared by setting the fifo-clr bit (bit 4) in the iso-fifo control register (address 0eh) to 1. given below is a timing chart for the isochronous interface when the fifo buffer is cleared. note that this fifo buffer clear function is available only when the point-rec bit (bit 7) or length-chk bit (bit 6) in the iso-fifo control register has been set to 1. * : the iso transmission/reception fifo buffer is cleared while the ilwre signal is negated. parameter symbol value unit min. max. i v rise to i lwre rise t clr 4 t iclk ns ilwre negate time t wreh 7 t iclk ns ilwre iv t clr t wreh
42 mb86615 n internal registers the mb86615 internal registers have 3-bank construction, with 16-bit access to all registers. bank 0 contains registers necessary for ieee 1394 settings and transfer, bank 1 contains registers necessary for av/c (dvc) operation, and bank 2 contains csrs. in addition each bank has registers used in common for mb86615 device control. 1. bank common registers the following registers can be accessed in any bank from bank 0 to bank 2. address write operation read operation hexa5a4a3a2a1 00 0 0 0 0 0 mode-control register ? 02 0 0 0 0 1 (reserved) flag & status register 04 0 0 0 1 0 instruction fetch register ? 06 0 0 0 1 1 interrupt mask register interrupt code register 08 0 0 1 0 0 (reserved) receiving acknowledge display register 0a 0 0 1 0 1 async data port (sending) async data port (receiving) 0c 0 0 1 1 0 mode-control-2 register ? 0e 0 0 1 1 1 iso-fifo control register ? 3e 1 1 1 1 1 bank select register ?
43 mb86615 2. bank 0 registers bank 0 contains the registers required for 1394 settings and transfers. access to this bank is enabled by writing 0000h to the bank select register (3eh). address write operation read operation hexa5a4a3a2a1 1001000 sending iso pkt header setting register (high) receiving iso pkt header display register (high) 1201001 sending iso pkt header setting register (low) receiving iso pkt header display register (low) 1401010 sending async des id setting register receiving async des id setting register 1601011 sending async pkt param setting register receiving async pkt param display register 1801100 sending async data length setting register receiving async data length display register 1a01101 sending async ex tcode setting register receiving async ex tcode display register 1c01110 sending async source id setting register receiving async source id display register 1e01111 sending async resp param setting register receiving async resp param display register 2010000 sending async des offset setting register (high) receiving async des offset display register (high) 2210001 sending async des offset setting register (middle) receiving async des offset display register (middle) 2410010 sending async des offset setting register (low) receiving async des offset display register (low) 26 1 0 0 1 1 (reserved) ? 28 1 0 1 0 0 (reserved) phy id display register 2a 1 0 1 0 1 (reserved) node config display register 2c 1 0 1 1 0 (reserved) ? 2e 1 0 1 1 1 (reserved) port config display register 30 1 1 0 0 0 state clear setting register root id display register 32 1 1 0 0 1 self id pkt param setting register iso resource manager id display register 3411010 receiving iso-channel setting register (0, 1) ? 3611011 receiving iso-channel setting register (2, 3) ? 38 1 1 1 0 0 (reserved) cycle timer monitor display register (high) 3a 1 1 1 0 1 (reserved) cycle timer monitor display register (low) 3c 1 1 1 1 0 (reserved) ?
44 mb86615 3. bank 1 registers bank 1 contains the registers required for av/c (dvc) protocols. access to this bank is enabled by writing 0001h to the bank select register (3eh). address write operation read operation hexa5a4a3a2a1 1001000 sending time stamp offset setting register ? 1201001 receiving time stamp offset setting register ? 1401010 sending cip header dbs setting register receiving cip header display register (highest) 16 0 1 0 1 1 (reserved) receiving cip header display register (high) 1801100 sending cip header fmt setting register receiving cip header display register (low) 1a 0 1 1 0 1 (reserved) receiving cip header display register (lowest) 1c01110 ompr (high) ? 1e01111 ompr (low) ? 2010000 opcr0 (high) ? 2210001 opcr0 (low) ? 24 1 0 0 1 0 (reserved) ? 26 1 0 0 1 1 (reserved) ? 28 1 0 1 0 0 (reserved) ? 2a 1 0 1 0 1 (reserved) ? 2c10110 impr (high) ? 2e10111 impr (low) ? 3011000 ipcr0 (high) ? 3211001 ipcr0 (low) ? 34 1 1 0 1 0 (reserved) ? 36 1 1 0 1 1 (reserved) ? 38 1 1 1 0 0 (reserved) ? 3a 1 1 1 0 1 (reserved) ? 3c 1 1 1 1 0 set-pcr & fp-timeout setting register ?
45 mb86615 4. bank 2 registers bank 2 contains csrs required for isochronous resource manager. access to this bank is enabled by writing 0002h to the bank select register (3eh). address write operation read operation hexa5a4a3a2a1 10 0 1 0 0 0 bus manager id register (high) ? 12 0 1 0 0 1 bus manager id register (low) ? 14 0 1 0 1 0 bandwidth available register (high) ? 16 0 1 0 1 1 bandwidth available register (low) ? 18 0 1 1 0 0 channels available high register (high) ? 1a 0 1 1 0 1 channels available high register (low) ? 1c 0 1 1 1 0 channels available low register (high) ? 1e 0 1 1 1 1 channels available low register (low) ? 20 1 0 0 0 0 (reserved) ? 22 1 0 0 0 1 (reserved) ? 24 1 0 0 1 0 (reserved) ? 26 1 0 0 1 1 (reserved) ? 28 1 0 1 0 0 (reserved) ? 2a 1 0 1 0 1 (reserved) ? 2c 1 0 1 1 0 (reserved) ? 2e 1 0 1 1 1 (reserved) ? 30 1 1 0 0 0 (reserved) ? 32 1 1 0 0 1 (reserved) ? 34 1 1 0 1 0 (reserved) ? 36 1 1 0 1 1 (reserved) ? 38 1 1 1 0 0 (reserved) ? 3a 1 1 1 0 1 (reserved) ? 3c 1 1 1 1 0 (reserved) ?
46 mb86615 n ordering information partnumber package remarks mb86615pfv 100-pin plastic lqfp (fpt-100p-m05) MB86615PBT 120-pin plastic fbga (bga-120p-m01)
47 mb86615 n package dimensions 100-pin plastic lqfp (fpt-100p-m05) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. (mounting height) dimensions in mm (inches) 120-pin plastic fbga (bga-120p-m01) c 1998 fujitsu limited b120001s-1c-1 12.00?.10(.472?004)sq .049 ?004 +.008 ?.10 +0.20 1.25 (mounting height) 0.38?.10(.015?004) (stand off) 0.10(.004) c0.80(.031) index 9.60(.378)ref 0.80(.031)typ 1 2 3 4 5 6 7 8 9 10 11 lkjhgfedcba 120-0.45?.10 (120-.018?004) m 0.08(.003) 12 13 m n dimensions in mm (inches)
48 mb86615 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9902 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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